74LS196-Presetable Decade Counter
The 74LS series of integrated circuits (ICs) was one of the most popular logic families of transistor-transistor logic (TTL) logic chips. 74LS series is a bipolar, low-power Schottky IC. The 74LS196 decade counter is partitioned into divide-by-two and divide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1) sequence or in a bi-quinary mode producing a 50% duty cycle output
74LS196 Features
- Asynchronous Presettable
- Asynchronous Master Reset
- Easy Multistage Cascading
- Input Clamp Diodes Limit High Speed Termination Effects
74LS196 Specifications
| Supply Voltage | 4.75 - 5.25Vdc |
| Maximum Clock Frequency | 40Mhz |
| Power Dissipation | 2mW/gate @100kHz |
| Minimum Output Current | 8mA |
| Propagation Delay | 10nS |
| Fan Out (TTL Loads) | 20 |
74LS196 Pinout Diagram
74LS196 Pin Description
| Pin No | Pin Name | Description |
| 1 | LOAD' | Load Pin(Active Low) |
| 2 | QC | Output Pin |
| 3 | C | Data Input Pin |
| 4 | A | Data Input Pin |
| 5 | QA | Output Pin |
| 6 | CLK 2 | Clock Pin 2 |
| 7 | GND | Ground |
| 8 | CLK 1 | Clock Pin 1 |
| 9 | QB | Output Pin |
| 10 | B | Data Input Pin |
| 11 | D | Data Input Pin |
| 12 | QD | Output Pin |
| 13 | CLR' | Clear Pin(Active Low) |
| 14 | VCC | Positive Supply |
Applications
- Clock generation
- Clock division
- Integrated oscillator
- Low power CMOS
- TTL compatible inputs
- In frequency counting circuits
74LS196 Alternative Equivalent
Download 74LS196-Presetable Decade Counter Datasheet from the link given below.
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